posted Nov 8, 2012, 6:30 AM by Neil Mathew
[
updated Nov 8, 2012, 6:15 PM
]
* Need to check if truth tables match with the NAND gates FLIP FLOP.
* The programs, never performed either by me either.
SR FLIP FLOP
| S | R | | Qnext | Comment |
|---|
| 0 | 0 | 0 | Hold state | | 0 | 1 | 0 | Reset | | 1 | 0 | 1 | Set | | 1 | 1 | Metastable |
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| LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY sr IS
port ( S,R, CLK: in std_logic; Q, Q2 : inout std_logic);
END ENTITY dff;
ARCHITECTURE sr2 OF dff IS
BEGIN
PROCESS(CLK)
BEGIN
IF RISING_EDGE(CLK) THEN
IF S='0' AND R='0' THEN
Q <= Q;
Q2 <= Q2;
ELSIF S='0' AND R='1' THEN
Q <= '0';
Q2 <= '1';
ELSIF S='1' AND R='0' THEN
Q <= '1';
Q2 <= '0';
ELSIF S='1' AND R='1' THEN
Q <= 'X';
Q2 <= 'X';
END IF;
END IF;
END PROCESS;
END ARCHITECTURE dff2;
|
D FLIP FLOP
| D | | Qnext | Comment |
|---|
| 0 | 0 | Express D atQ | | 1 | 1 | Express D atQ | | X | Qprev | Hold state
|
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| LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY dff IS
port(D, clk : in std_logic; Q, Qbar: out std_logic);
END ENTITY dff;
ARCHITECTURE dff2 OF dff IS
BEGIN
process(Clk)
Begin
if RISING_EDGE(Clk) then
Q<= D;
Qbar<= not D;
end if;
end process;
END ARCHITECTURE dff2;
|
J K FLIP FLOP
| Characteristic table | | J | K | | Qnext | Comment |
|---|
| 0 | 0 | Qprev | Hold state | | 0 | 1 | 0 | Reset | | 1 | 0 | 1 | Set | | 1 | 1 | Qprev | Toggle |
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| LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY jkff IS
port( J,K,clk: in std_logic;
Q, Qbar : inout std_logic);
END ENTITY jkff;
ARCHITECTURE jkff12 OF jkff IS
BEGIN
process (clk)
Begin
if RISING_EDGE(clk) then
if J='0' and K='0' then
null;
elsif J='0' and K='1' then
Q<='0';
Qbar<='1';
elsif J= '1' and K='0' then
Q<='1';
Qbar<='0';
elsif J='1' and K='1' then
Q<=not Q;
Qbar<=Q;
end if;
end if;
end process;
END ARCHITECTURE jkff12;
|
T FLIP FLOP
| T | Q | | Qnext | Comment |
|---|
| 0 | 0 | 0 | Hold state | | 0 | 1 | 1 | | 1 | 0 | 1 | Toggle | | 1 | 1 | 0 |
| |
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| LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY T_1 IS
port ( CLOCK: in std_logic; Q, T: in std_logic;
QNEXT: out std_logic);
END ENTITY T_1;
ARCHITECTURE TFF OF T_1 IS
SIGNAL QTEMP: std_logic;
BEGIN
QNEXT<=QTEMP;
PROCESS(CLOCK)
BEGIN
IF RISING_EDGE(CLOCK) THEN
if(T='0' AND Q='0') then
QTEMP<='0';
elsif(T='0' AND Q='1') then
QTEMP<='1';
elsif(T='1' AND Q='0') then
QTEMP<='1';
else
QTEMP<= '0';
end if;
end if;
end process;
END ARCHITECTURE TFF;
|
| T | | Qnext | Comment |
|---|
| 0 | Q | Hold state | | 1 | Q ' | Toggle |
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| IF RISING_EDGE(CLOCK) THEN
ifT='0' then
Q<=Q; QBar=Qbar;
else
Q<= Qbar; Qbar<= Q; end if;
end if;
end process;
END ARCHITECTURE TFF;
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