Sem 5‎ > ‎VHDL LAB‎ > ‎

Flip Flops

posted Nov 8, 2012, 6:30 AM by Neil Mathew   [ updated Nov 8, 2012, 6:15 PM ]

    * Need to check if truth tables match with the NAND gates FLIP FLOP.

    * The programs, never performed either by me either.


SR FLIP FLOP


SRQnextComment
000Hold state
010Reset
101Set
11Metastable
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
 
 
ENTITY sr IS
port ( S,R, CLK: in std_logic; Q, Q2 : inout std_logic);
END ENTITY dff;
 
ARCHITECTURE sr2 OF dff IS
BEGIN
 
    PROCESS(CLK)
    BEGIN
 
    IF RISING_EDGE(CLK) THEN
 
      IF S='0' AND R='0' THEN
      Q <= Q;
      Q2 <= Q2;
      ELSIF S='0' AND R='1' THEN
      Q <= '0';
      Q2 <= '1';
      ELSIF S='1' AND R='0' THEN
      Q <= '1';
      Q2 <= '0';
      ELSIF S='1' AND R='1' THEN
      Q <= 'X';
      Q2 <= 'X';           
      END IF;
 
    END IF;
    END PROCESS;    
END ARCHITECTURE dff2;



D FLIP FLOP



DQnextComment
00Express D atQ
11Express D atQ
XQprevHold state


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
 
ENTITY dff IS
port(D, clk : in std_logic; Q, Qbar: out std_logic);
END ENTITY dff;
 
ARCHITECTURE dff2 OF dff IS
BEGIN
  process(Clk)
  Begin
 
  if RISING_EDGE(Clk) then
    Q<= D;
    Qbar<= not D;
    end if;
 
    end process;
 
END ARCHITECTURE dff2;
 



J K FLIP FLOP


Characteristic table
JKQnextComment
00QprevHold state
010Reset
101Set
11QprevToggle

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
 
 
ENTITY jkff IS
 
port( J,K,clk: in std_logic; 
Q, Qbar : inout std_logic);
 
END ENTITY jkff;
 
ARCHITECTURE jkff12 OF jkff IS
BEGIN
  process (clk)
  Begin
 
    if RISING_EDGE(clk) then
 
      if J='0' and K='0' then
        null;
 
      elsif J='0' and K='1' then
      Q<='0';
      Qbar<='1';
 
      elsif J= '1' and K='0' then
        Q<='1';
        Qbar<='0';
 
      elsif J='1' and K='1' then
        Q<=not Q;
        Qbar<=Q;
 
      end if;
      end if;
 
      end process;
    END ARCHITECTURE jkff12;




T FLIP FLOP


TQQnextComment
000Hold state
011
101Toggle
110

report bug / make suggestion
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
 
ENTITY T_1 IS
port ( CLOCK: in std_logic; Q, T: in std_logic;
       QNEXT: out std_logic);
END ENTITY T_1;
 
ARCHITECTURE TFF OF T_1 IS
SIGNAL QTEMP: std_logic;
BEGIN
 
QNEXT<=QTEMP;
 
PROCESS(CLOCK)
BEGIN
 
IF RISING_EDGE(CLOCK) THEN
 
        if(T='0' AND Q='0') then
        QTEMP<='0';
        elsif(T='0' AND Q='1') then
        QTEMP<='1';
        elsif(T='1' AND Q='0') then
        QTEMP<='1';
        else
        QTEMP<= '0';
 
        end if;
 
end if;
end process;
  
END ARCHITECTURE TFF;
 

TQnextComment
0QHold state
1Q 'Toggle
    
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
IF RISING_EDGE(CLOCK) THEN
 
        ifT='0' then
        Q<=Q; 
        QBar=Qbar;
      else
        Q<= Qbar;
       Qbar<= Q;
        end if;   end if; end process;   END ARCHITECTURE TFF;  



Comments