Sem 5‎ > ‎VHDL LAB‎ > ‎

E1 : VHDL code to count ones in a vector array of 8 bits.

posted Nov 17, 2012, 10:42 PM by Neil Mathew

SOURCE CODE:

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library IEEE;
use IEEE.STD_LOGIC_1164.all;  
use IEEE.STD_LOGIC_unsigned.all;  
 
entity count_ones_en is
    port( Sin: in std_logic_vector( 7 downto 0 );
                  count: out integer );
end count_ones_en;
 
 
 
architecture arch of count_ones_en is
begin
        
        process(Sin)
        variable temp: Integer:=0;
        begin                                     
                
                labelloop: for i in 0 to 7 loop
                        if( sin(i) = '1') then            
                                temp := temp + 1;  
                        end if;
                end loop;
        
                COUNT <= temp;
        end process;
end arch;
 





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