I'm comparing the three using a 2:1 MUX example. 

The three styles are different by some syntax (change or addition in code) and implementation when it comes to concept (like use of IF statements in Behavioural, or use of existing components in Structural)

 

(Also, mentioning, VHDL is NOT case sensitive.)

DataFlow	Behavioural	Structural
-- DataFlow LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY mux2isto4 IS port(a,b,s:in std_logic;       y   :out std_logic); END ENTITY mux2isto4; ARCHITECTURE mux2isto4_a OF mux2isto4 IS   BEGIN   y <= ((not s) and a)           or (s and b); END ARCHITECTURE mux2isto4_a;	-- Behavioural LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY mux2isto4 IS port(a,b,s:in std_logic;       y   :out std_logic); END ENTITY mux2isto4; ARCHITECTURE mux2isto4_a OF mux2isto4 IS     BEGIN  PROCESS(a,b,s) BEGIN    if( s= '0' ) then         y <= a; else        y <= b; end if;    END PROCESS; END ARCHITECTURE mux2isto4_a;	-- Structural LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY mux2isto4 IS port(a,b,s:in std_logic;        y   :out std_logic); END ENTITY mux2isto4; ARCHITECTURE mux2isto4_a OF mux2isto4 IS --components and signals BEFORE begin component and2   port(a,b:in std_logic;        y:out std_logic); end component;           component not1 port(a:in std_logic;      b: out std_logic); end component; component or2 port(a,b:in std_logic;        y:out std_logic); end component; signal a_and_nots, not_s, b_and_s : std_logic; BEGIN Invert_S:               not1 port map(s,not_s); An_And_Operation:       and2 port map(a, not_s,  a_and_nots); Another_And_Operation:  and2 port map(s,b,b_and_s); Final_Or_Operation:     or2 port map(a_and_nots,b_and_s,y);       END ARCHITECTURE mux2isto4_a;