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VHDL LAB

E2: Write a program to take an input serial bit stream and outputs a '1' whenever the sequence "01010" occurs overlap must also be considered.

posted Nov 17, 2012, 11:18 PM by Neil Mathew

Although compiled, untested. :/


SOURCE CODE:

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library IEEE;
use IEEE.STD_LOGIC_1164.all;       
use IEEE.std_logic_arith.all;
 
entity pattern_find_en is
        port( Sin: in bit; -- serial input bit
                  Sout: out bit); -- outputs 1 if "01010" occurs
end pattern_find_en;
 
 
architecture arch of pattern_find_en is
signal temp: bit_vector(4 downto 0); -- can be variable too
begin
        
        process( Sin )
        variable count: integer := 0;   
        begin
                
                -- At first, it fills up till 5 input bits are available for check.
                -- shifts values towards the right, and keeps adding the new bit for check
                        
                        if count=0 then
                                temp(0) <= Sin;
                                count:=count+1;
                        elsif count < 5 then
                                temp <= temp srl 1;
                                temp(0) <= Sin;
                                count:=count+1;
                        else
                                temp <= temp srl 1;
                                temp(0) <= Sin;
                        end if;
                                
                -- the check
                
                if temp = "01010" then
                        Sout <= '1';
                else 
                        Sout <= '0';
                end if;
        end process;
end arch;
 





E1 : VHDL code to count ones in a vector array of 8 bits.

posted Nov 17, 2012, 10:42 PM by Neil Mathew


SOURCE CODE:

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library IEEE;
use IEEE.STD_LOGIC_1164.all;  
use IEEE.STD_LOGIC_unsigned.all;  
 
entity count_ones_en is
    port( Sin: in std_logic_vector( 7 downto 0 );
                  count: out integer );
end count_ones_en;
 
 
 
architecture arch of count_ones_en is
begin
        
        process(Sin)
        variable temp: Integer:=0;
        begin                                     
                
                labelloop: for i in 0 to 7 loop
                        if( sin(i) = '1') then            
                                temp := temp + 1;  
                        end if;
                end loop;
        
                COUNT <= temp;
        end process;
end arch;
 





Flip Flops

posted Nov 8, 2012, 6:30 AM by Neil Mathew   [ updated Nov 8, 2012, 6:15 PM ]


    * Need to check if truth tables match with the NAND gates FLIP FLOP.

    * The programs, never performed either by me either.


SR FLIP FLOP


SRQnextComment
000Hold state
010Reset
101Set
11Metastable
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LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
 
 
ENTITY sr IS
port ( S,R, CLK: in std_logic; Q, Q2 : inout std_logic);
END ENTITY dff;
 
ARCHITECTURE sr2 OF dff IS
BEGIN
 
    PROCESS(CLK)
    BEGIN
 
    IF RISING_EDGE(CLK) THEN
 
      IF S='0' AND R='0' THEN
      Q <= Q;
      Q2 <= Q2;
      ELSIF S='0' AND R='1' THEN
      Q <= '0';
      Q2 <= '1';
      ELSIF S='1' AND R='0' THEN
      Q <= '1';
      Q2 <= '0';
      ELSIF S='1' AND R='1' THEN
      Q <= 'X';
      Q2 <= 'X';           
      END IF;
 
    END IF;
    END PROCESS;    
END ARCHITECTURE dff2;



D FLIP FLOP



DQnextComment
00Express D atQ
11Express D atQ
XQprevHold state


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LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
 
ENTITY dff IS
port(D, clk : in std_logic; Q, Qbar: out std_logic);
END ENTITY dff;
 
ARCHITECTURE dff2 OF dff IS
BEGIN
  process(Clk)
  Begin
 
  if RISING_EDGE(Clk) then
    Q<= D;
    Qbar<= not D;
    end if;
 
    end process;
 
END ARCHITECTURE dff2;
 



J K FLIP FLOP


Characteristic table
JKQnextComment
00QprevHold state
010Reset
101Set
11QprevToggle

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LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
 
 
ENTITY jkff IS
 
port( J,K,clk: in std_logic; 
Q, Qbar : inout std_logic);
 
END ENTITY jkff;
 
ARCHITECTURE jkff12 OF jkff IS
BEGIN
  process (clk)
  Begin
 
    if RISING_EDGE(clk) then
 
      if J='0' and K='0' then
        null;
 
      elsif J='0' and K='1' then
      Q<='0';
      Qbar<='1';
 
      elsif J= '1' and K='0' then
        Q<='1';
        Qbar<='0';
 
      elsif J='1' and K='1' then
        Q<=not Q;
        Qbar<=Q;
 
      end if;
      end if;
 
      end process;
    END ARCHITECTURE jkff12;




T FLIP FLOP


TQQnextComment
000Hold state
011
101Toggle
110

report bug / make suggestion
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LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
 
ENTITY T_1 IS
port ( CLOCK: in std_logic; Q, T: in std_logic;
       QNEXT: out std_logic);
END ENTITY T_1;
 
ARCHITECTURE TFF OF T_1 IS
SIGNAL QTEMP: std_logic;
BEGIN
 
QNEXT<=QTEMP;
 
PROCESS(CLOCK)
BEGIN
 
IF RISING_EDGE(CLOCK) THEN
 
        if(T='0' AND Q='0') then
        QTEMP<='0';
        elsif(T='0' AND Q='1') then
        QTEMP<='1';
        elsif(T='1' AND Q='0') then
        QTEMP<='1';
        else
        QTEMP<= '0';
 
        end if;
 
end if;
end process;
  
END ARCHITECTURE TFF;
 

TQnextComment
0QHold state
1Q 'Toggle
    
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IF RISING_EDGE(CLOCK) THEN
 
        ifT='0' then
        Q<=Q; 
        QBar=Qbar;
      else
        Q<= Qbar;
       Qbar<= Q;
        end if;   end if; end process;   END ARCHITECTURE TFF;  



03 Importing Other's work into your own project

posted Aug 22, 2012, 12:35 PM by Neil Mathew   [ updated Aug 22, 2012, 12:42 PM ]



When you're doing the structural style, you realize you need to create the smaller components like and2, xor2, etc, which are usually already made by others who were in the lab before you. These are instructions to easily import these gates into your own project.

Step 0: If you're keen on doing it yourself, this image explains how to add a new component.



Step 1: To make your job a lot easier, choose Add, instead of New.



Step 2: Search for the components you need, and on selecting them, click Ok



I should mention that to avoid DATA BINDING issues, make sure the input and output signals of t the he component mentioned in the Structural Style Program should be named the same as that in components you've added.

That is, if this code snippet is there in your Structural Style program:

      component and2
        port(a,b:in std_logic;
             y:out std_logic);
      end component;

Then, the and2 component you're using should have a, b as it's input and y as it's output as specified in the entity. (that is, having x,y,z as the names would give you an error)

ENTITY AND2 IS

  PORT( A,B : IN  STD_LOGIC;

          Y : OUT STD_LOGIC );

END ENTITY AND2;



ENTITY NM_EN IS

  PORT( W,X : IN  STD_LOGIC;

          Z : OUT STD_LOGIC );

END ENTITY NM_EN;

00 Compare DataFlow, Behavioural, Structural

posted Aug 22, 2012, 12:22 PM by Neil Mathew   [ updated Aug 22, 2012, 12:25 PM ]


I'm comparing the three using a 2:1 MUX example. 
The three styles are different by some syntax (change or addition in code) and implementation when it comes to concept (like use of IF statements in Behavioural, or use of existing components in Structural)
 
(Also, mentioning, VHDL is NOT case sensitive.)

 DataFlow     Behavioural     Structural 
-- DataFlow

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;


ENTITY mux2isto4 IS
port(a,b,s:in std_logic;
      y   :out std_logic);
END ENTITY mux2isto4;



ARCHITECTURE mux2isto4_a
OF mux2isto4 IS


 

BEGIN
 
y <= ((not s) and a)
          or (s and b);




END ARCHITECTURE mux2isto4_a; 
-- Behavioural

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;


ENTITY mux2isto4 IS
port(a,b,s:in std_logic;
      y   :out std_logic);
END ENTITY mux2isto4;



ARCHITECTURE mux2isto4_a
OF mux2isto4 IS
 

 

BEGIN 

PROCESS(a,b,s)
BEGIN
  
if( s= '0' ) then  
      y <= a;
else 
      y <= b;
end if;
  

END PROCESS;

END ARCHITECTURE mux2isto4_a;
-- Structural

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;


ENTITY mux2isto4 IS
port(a,b,s:in std_logic;
       y   :out std_logic);
END ENTITY mux2isto4;



ARCHITECTURE mux2isto4_a OF mux2isto4 IS


--components and signals BEFORE begin

component and2
  port(a,b:in std_logic;
       y:out std_logic);
end component;
         
component not1
port(a:in std_logic;
     b: out std_logic);
end component;

component or2
port(a,b:in std_logic;
       y:out std_logic);
end component;


signal a_and_nots, not_s, b_and_s : std_logic;

BEGIN

Invert_S:               not1 port map(s,not_s);

An_And_Operation:       and2 port map(a, not_s, 
a_and_nots);

Another_And_Operation:  and2 port map(s,b,b_and_s);

Final_Or_Operation:     or2 port map(a_and_nots,b_and_s,y);
     

END ARCHITECTURE mux2isto4_a; 




02 Program, Compile & RUN

posted Aug 22, 2012, 11:52 AM by Neil Mathew   [ updated Aug 22, 2012, 12:01 PM ]


Step 1: Double click on the component to edit


Step 2: Type the program. Screenshot that of an AND gate component.




Step 3: Once the program is done, Look for the below toolbar. 
            The green tick on document icon basically compiles it (DesignChecker).




And if there are no errors, it should give this:



Step 4: Once that's done, look for the same toolbar and look for the M icon to start ModelSim Simulator.





Step 5: If you're starting ModelSim for the first time, you'll see this window. Just click ok.

   


Step 6: Now, the ModelSim window should appear.
            However, the Objects and Waveform window may not always appear with it.
            In such cases, Click VIEW from the menu and select Objects and Wave



Step 7: In the object window, add the signals to the Wave as shown:




Step 8: Next, either FORCE values to the signals or define a CLOCK.

            Right-click on a signal, 

            i) FORCE a value to a signal. Click Force. Then specify value.

   

   

            ii) DEFINE CLOCK for a signal. Click Clock. Then specify the period. 
                I find it easier to specify periods in multiples of 2. If a is set to 50, 
                then setting b to 100 gives a rather clear picture of the waves.

   



Step 9: Finally, Click the RUN button highlighted by the red circle. 
            The waves should appear then.


01 Creating a project in FPGA Advantage 8.1

posted Aug 22, 2012, 11:31 AM by Neil Mathew


Step 1: Look FPGA Advantage 8.1 LS PS up from the Start Menu and click it.


Step 2: File > New > Project


Step 3: Specify Name of Project


Step 4: Next, Next, Finish...


Step 5: Specify VHDL File (as Category) and Combined (as File Type)


Step 6:
 Name the Entity and Architecture of your new project. 
            (both of them can share the same name)




And Voila! 



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